SRAM Chip Async Single 5V 256K-Bit 64K x 4-Bit 12ns 28-Pin SOJ

The CY7C195 are high-performance CMOS static RAMs organized as 65,536 by 4 bits. Easy memory expansion is provided by active LOW Chip Enable(s) (CE on the CY7C195, CE1/, CE2/) and three-state drivers. They have an automatic power-down feature, reducing the power consumption by 75% when deselected. Writing to the device is accomplished when the Chip Enable(s) (CE/ on the CY7C195, CE1/, CE2/) and Write Enable (WE/) inputs are both LOW. Data on the four input pins (I/O0 through I/O3) is written into the memory location, specified on the address pins (A0 through A15).The device is accomplished by taking the Chip Enable(s) (CE/ on the CY7C195, CE1/, CE2/) LOW, while Write Enable (WE/) remains HIGH. Under these conditions the contents of the memory location specified on the address pins will appear on the four data I/O pins. A die coat is used to ensure alpha immunity.

• High speed: 12 ns
• Output enable (OE/) feature (7C195)
• CMOS for optimum speed/power
• Low active power: 880 mW
• Low standby power: 220 mW
• TTL-compatible inputs and outputs
• Automatic power-down when deselected