SRAM Chip Async Single 5V 256K-Bit 32K x 8 70ns 32-Pin TSOP-I

The M5M5256DVP is 262,144-bit CMOS static RAMs organized as 32,768-words by 8-bits which is fabricated using high-performance 3 polysilicon CMOS technology. The use of resistive load NMOS cells and CMOS periphery results in a high density and low power static RAM. Stand-by current is small enough for battery back-up application. It is ideal for the memory systems which require simple interface.Especially the M5M5256DVP is packaged in a 28-pin thin small outline package.M5M5256DVP (normal lead bend type package).Using this type of device, it becomes very easy to design a printed circuit board.

• Power supply current
  • Active (max): 55mA (Vcc=5.5V)
  • Stand-by (max): 20µA (Vcc=5.5V), 5µA (Vcc=5.5V), 0.05µA (Vcc=3.0V, Typical)
• Single +5V power supply
• No clocks, no refresh
• Data-Hold on +2.0V power supply
• Directly TTL compatible : all inputs and outputs
• Three-state outputs : OR-tie capability
• /OE prevents data contention in the I/O bus
• Common Data I/O
• Battery backup capability
• Low stand-by current: 0.05µA(typ.)