SRAM Chip Sync Quad 3.3V 36M-Bit 1M x 36 6.5ns 100-Pin TQFP Tray

The CY7C1461AV33 is 3.3 V, 1 M × 36/2 M × 18 Synchronous Flow-Through Burst SRAMs designed specifically to support unlimited true back-to-back read and write operations without the insertion of wait states. The CY7C1461AV33/CY7C1463AV33 is equipped with the advanced NoBL logic required to enable consecutive read and write operations with data being transferred on every clock cycle.

• No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
• Supports up to 133 MHz bus operations with zero wait states
  • Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™ devices
• Internally self timed output buffer control to eliminate the need to use
• Registered inputs for flow through operation
• Byte write capability
• 3.3 V and 2.5 V I/O power supply
• Fast clock-to-output times
  • 6.5 ns (for 133 MHz device)
• Clock Enable (CE/ and OE/?) pin to enable clock and suspend operation
• Synchronous self timed writes
• Asynchronous Output Enable
• CY7C1461AV33, CY7C1463AV33 available in JEDEC-standard Pb-free 100-pin TQFP package.
• Three chip enables for simple depth expansion
• Automatic power down feature available using ZZ mode or CE deselect
• Burst capability - linear or interleaved burst order
• Low standby power