SRAM Chip Sync Quad 3.3V 2M-Bit 64K x 36 3.5ns 100-Pin TQFP

The CY7C1346H SRAM integrates 64K x 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input. The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable, depth-expansion Chip Enables, Burst Control inputs, Write Enables, and Global Write. Asynchronous inputs include the Output Enable and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor or Address Strobe Controller are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin. Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations. Write cycles can be one to four bytes wide as controlled by the Byte Write control inputs. GW when active LOW causes all bytes to be written. The CY7C1346H operates from a +3.3V core power supply while all outputs also operate with either a +3.3V/2.5V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.

• Registered inputs and outputs for pipelined operation
• 64K × 36 common I/O architecture
• 3.3V core power supply
• 3.3V/2.5V I/O operation
• Fast clock-to-output times
  • 3.5 ns (166-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Offered in JEDEC-standard lead-free 100-pin TQFP package
• “ZZ” Sleep Mode Option