SRAM Chip Sync Dual 2.5V/3.3V 18M-Bit 1M x 18 5.5ns/2.5ns 165-Pin FBGA Tray
SRAM Chip Sync Dual 2.5V/3.3V 18M-Bit 1M x 18 5.5ns/2.5ns 165-Pin FBGA Tray
- FT pin for user-configurable flow through or pipeline operation
- Single Cycle Deselect (SCD) operation
- IEEE 1149.1 JTAG-compatible Boundary Scan
- 2.5 V or 3.3 V +10%/–10% core power supply
- 2.5 V or 3.3 V I/O supply
- LBO pin for Linear or Interleaved Burst mode
- Internal input resistors on mode pins allow floating mode pins
- Default to Interleaved Pipeline mode
- Byte Write (BW) and/or Global Write (GW) operation
- Internal self-timed write cycle
- Automatic power-down for portable applications
- JEDEC-standard 100-lead TQFP 100-pin TQFP and 165-bump BGA packages
- RoHS-compliant 100-pin TQFP and 165-bump BGA packages available
- 3rd Generation, 13 mm x 15 mm, 165 FPBGA
Especificações
| Brand | GSI Technology |
|---|---|
| Datasheet | |
| Timing Type | Synchronous |
| Number Of Words | 1 MWords |
| Density | 18 Mbit |
| Operating temperature | -40 to 85 °C |
| Pin Count | 165 |
| Number Of Ports | 2 |
| Mounting | Surface Mount |
| Number Of | 18 Bit |
| Product description | 15 x 13 x 0.94 mm |
| Typical O | 2.5, 3.3 V |
| ECCN | 3A991.B.2.B |
| Schedule B | 8542320040 |
| HTSN | 8542320041 |
| Minimum O | 2.3, 3 V |
| Maximum O | 2.7, 3.6 V |
| Data Rate | SDR |
| Architecture | Flow-Through|Pipelined |
| Lead Finish | Tin/Lead |
SKU: GS816118BD-250I