SRAM Chip Sync Dual 1.8V/2.5V 36M-Bit 2M x 18 5ns/3ns 100-Pin TQFP

The GS832018AGT is a 37,748,736-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.

• FT pin for user-configurable flow through or pipeline operation
• Single Cycle Deselect (SCD) operation
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• RoHS-compliant 100-lead TQFP package
• 32MB or 36MB product family
• Green TQFP
• Default to SCD x18 Interleaved Pipeline mode