SRAM Chip Sync Dual 1.8V 36M-Bit 4M x 8 0.45ns 165-Pin FBGA Tray

The CY7C1411KV18 is 1.8 V synchronous pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations.

• Separate independent read and write data ports
  • Supports concurrent transactions
• 333 MHz clock for high bandwidth
• Four-word burst for reducing address bus frequency
• Double data rate (DDR) Interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
• Echo clocks (CQ and CQ) simplify data capture in high speed systems