SRAM Chip Async Single 3.3V 8M-Bit 512K x 16 12ns 44-Pin TSOP-II T/R

The CY7C1051DV33 is a high performance CMOS Static RAM organized as 512 K words by 16-bits. To write to the device, take Chip Enable and Write Enable inputs LOW. If Byte LOW Enable is LOW, then data from I/O pins (I/O0–I/O7), is written into the location specified on the address pins (A0–A18). If Byte HIGH Enable is LOW, then data from I/O pins (I/O8–I/O15) is written into the location specified on the address pins (A0–A18). To read from the device, take Chip Enable and Output Enable LOW while forcing the Write Enable HIGH. If Byte LOW Enable is LOW, then data from the memory location specified by the address pins appears on I/O0–I/O7. If Byte HIGH Enable is LOW, then data from memory appears on I/O8 to I/O15. See the Truth Table on page 10 for a complete description of read and write modes. The input/output pins (I/O0–I/O15) are placed in a high-impedance state when the device is deselected , the outputs are disabled , a write operation is in progress. The CY7C1051DV33 is available in a 44-pin TSOP II package with center power and ground (revolutionary) pinout and a 48-ball FBGA package.

• Temperature ranges
  • -40 °C to 85 °C
• High speed
  • tAA = 10 ns
• Low active power
  • ICC = 110 mA at f = 100 MHz
• Low CMOS standby power
  • ISB2 = 20 mA
• 2.0-V data retention
• Automatic power-down when deselected
• Transistor-transistor logic (TTL)-compatible inputs and outputs
• Easy memory expansion with CE and OE features
• Available in Pb-free 48-ball fine ball grid array (FBGA) and 44-pin thin small outline package (TSOP) II packages