SRAM Chip Async Single 2.5V/3.3V/5V 32M-Bit 4M/2M x 8/16-Bit 55ns 48-Pin TSOP-I Tray

The CY62177ESL is a high performance CMOS static RAM organized as 2 M words by 16 bits and 4 M words by 8 bits. This device features advanced circuit design to provide ultra low active current. It is ideal for providing More Battery LifeTM (MoBL) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 99 percent when addresses are not toggling. The device can also be put into standby mode when deselected. The input and output pins are placed in a high impedance state when: deselected, outputs are disabled, both Byte High Enable and Byte Low Enable are disabled, or during a write operation. To write to the device, take Chip Enables and Write Enable input LOW. If Byte Low Enable is LOW, then data from I/O pins, is written into the location specified on the address pins. If Byte High Enable is LOW, then data from I/O pins is written to the location specified on the address pins. To read from the device, take Chip Enables and Output Enable LOW while forcing the Write Enable HIGH. If Byte Low Enable is LOW, then data from the memory location specified by the address pins appear on I/O0 to I/O7. If Byte High Enable is LOW, then data from memory appears on I/O8 to I/O15.

• Thin small outline package-I (TSOP-I) configurable as 2 M × 16 or as 4 M × 8 static RAM (SRAM)
• High-speed up to 55 ns
• Wide voltage range: 2.2 V to 3.6 V and 4.5 V to 5.5 V
• Ultra low standby power
  • Typical standby current: 3 µA
  • Maximum standby current: 25 µA
• Ultra low active power
  • Typical active current: 4.5 mA at f = 1 MHz
• Easy memory expansion with CE1, CE2, and OE Features
• Automatic power-down when deselected
• Complementary metal oxide semiconductor (CMOS) for optimum speed and power
• Available in Pb-free 48-ball TSOP-I package