SRAM Chip Async Dual 5V 256K-Bit 256K x 1 25ns 24-Pin PDIP

The CY7C197N is a high-performance CMOS static RAM organized as 256 K words by 1 bit. Easy memory expansion is provided by an active LOW Chip Enable (CE) and three-state drivers. The CY7C197N has an automatic power-down feature, reducing the power consumption by 75% when deselected. Writing to the device is accomplished when the Chip Enable (CE) and Write Enable (WE) inputs are both LOW. Data on the input pin (DIN) is written into the memory location specified on the address pins (A0 through A17). Reading the device is accomplished by taking chip enable (CE) LOW while Write Enable (WE) remains HIGH. Under these conditions the contents of the memory location specified on the address pins will appear on the data output (DOUT) pin. The output pin stays in a high-impedance state when Chip Enable (CE) is HIGH or Write Enable (WE) is LOW. The CY7C197N uses a die coat to insure alpha immunity.

• High speed
  • 25 ns
• CMOS for optimum speed/power
• Low active power
  • 880 mW
• Low standby power
  • 220 mW
• Transistor-transistor logic (TTL)-compatible inputs and outputs
• Automatic power-down when deselected