SRAM Chip Async Dual 3.3V 512K-Bit 32K x 18 20ns 100-Pin TQFP Tray

The CY7037AV is low power CMOS 32K, 64K x 16/18 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as stand-alone 16/18-bit dual-port static RAMs or multiple devices can be combined to function as a 32/36-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 32/36-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include inter processor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory. Each port has independent control pins: Chip Enable (CE\), Read or Write Enable (R/W\), and Output Enable (OE\). Two flags are provided on each port (BUSY\ and INT\). BUSY\ signals that the port is trying to access the same location currently being accessed by the other port. The interrupt flag (INT\) permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power down feature is controlled independently on each port by a chip select (CE\) pin. The CY7037AV is available in 100-pin Thin Quad Plastic Flat packs (TQFP).

• True dual-ported memory cells which allow simultaneous access of the same memory location
• 32 K × 18 organization
• 0.35 micron Complementary metal oxide semiconductor (CMOS) for optimum speed and power
• High speed access: 15, 20, and 25 ns
• Low operating power
• Active: Icc = 115 mA (typical)
• Standby: Isb3 = 10 µA (typical)
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 32/36 bits or more using Master/Slave chip select when using more than one device
• On-chip arbitration logic
• Semaphores included to permit software handshaking between ports
• INT flag for port-to-port communication
• Separate upper-byte and lower-byte control
• Dual chip enables
• Pin select for Master or Slave
• Commercial and Industrial temperature ranges
• 100-pin Pb-free Thin quad plastic flatpack (TQFP) and 100-pin TQFP