SRAM Chip Async Dual 3.3V 512K-Bit 32K x 16 15ns 100-Pin TQFP

The CY7C027V is low power CMOS 32K, 64K x 16/18 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as stand-alone 16/18-bit dual-port static RAMs or mult iple devices can be combined to function as a 32/36-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 32/36-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multipro cessor designs, communications status buffering, and dual-port video/graphics memory.

• True dual-ported memory cells which allow simultaneous access of the same memory location
• 32 K × 16 organization (CY7C027V)
• 0.35 micron Complementary metal oxide semiconductor (CMOS) for optimum speed and power
• High speed access: 15, 20, and 25 ns
• Low operating power
• Active: ICC = 115 mA (typical)
• Standby: ISB3 = 10 µA (typical)
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 32/36 bits or more using Master/Slave chip select when using more than one device
• On-chip arbitration logic
• Semaphores included to permit software handshaking between ports
• ??T flag for port-to-port communication
• Separate upper-byte and lower-byte control
• Dual chip enables
• Pin select for Master or Slave
• Commercial and Industrial temperature ranges