SLC NAND Flash Parallel 3V/3.3V 4Gbit 512M x 8bit 63-Pin BGA Tray

The Spansion S34ML04G1 is offered in 3.3 VCC and VCCQ power supply, and with x8 or x16 I/O interface. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. The page size for x8 is (2048 + 64 spare) bytes; for x16 (1024 + 32) words. Each block can be programmed and erased up to 100,000 cycles with ECC (error correction code) on. To extend the lifetime of NAND flash devices, the implementation of an ECC is mandatory. The chip supports CE# don"t care function. This function allows the direct download of the code from the NAND flash memory device by a microcontroller, since the CE# transitions do not stop the read operation. The devices have a Read Cache feature that improves the read throughput for large files. During cache reading, the devices load the data in a cache register while the previous data is transferred to the I/O buffers to be read. Like all other 2-kB page NAND flash devices, a program operation typically writes 2112 bytes (x8), or 1056 words (x16) in 200 µs and an erase operation can typically be performed in 2 ms on a 128-kB block (x8) or 64-kword block (x16). In addition, thanks to multiplane architecture, it is possible to program two pages at a time (one per plane) or to erase two blocks at a time (again, one per plane). The multiplane architecture allows program time to be reduced by 40% and erase time to be reduced by 50%. In multiplane operations, data in the page can be read out at 25 ns cycle time per byte. The I/O pins serve as the ports for command and address input as well as data input/output. This interface allows a reduced pin count and easy migration towards different densities, without any rearrangement of the footprint. Commands, Data, and Addresses are asynchronously introduced using CE#, WE#, ALE, and CLE control pins. The on-chip Program/Erase Controller automates all read, program, and erase functions including pulse repetition, where required, and internal verification and margining of data. A WP# pin is available to provide hardware protection against program and erase operations. The output pin R/B# (open drain buffer) signals the status of the device during each operation. It identifies if the program/erase/read controller is currently active. The use of an open-drain output allows the Ready/Busy pins from several memories to connect to a single pull-up resistor. In a system with multiple memories the R/B# pins can be connected all together to provide a global status signal. The Reprogram function allows the optimization of defective block management — when a Page Program operation fails the data can be directly programmed in another page inside the same array section without the time consuming serial data insertion phase. The Copy Back operation automatically executes embedded error detection operation: 1-bit error out of every 528 bytes (x8) or 256 words (x16) can be detected. With this feature it is no longer necessary to use an external mechanism to detect Copy Back operation errors. Multiplane Copy Back is also supported. Data read out after Copy Back Read (both for single and multiplane cases) is allowed. In addition, Cache Program and Multiplane Cache Program operations improve the programing throughput by programing data using the cache register.

• Density
  • 1 Gbit / 2 Gbit / 4 Gbit
• Architecture
  • Input / Output Bus Width: 8-bits / 16-bits
  • Page Size:
  • x8 = 2112 (2048 + 64) bytes; 64 bytes is spare area
  • x16 = 1056 (1024 + 32) words; 32 words is spare area
  • Block Size: 64 Pages
  • x8 = 128k + 4k bytes
  • x16 = 64k + 2k words
  • Plane Size: 1 Gbit / 2 Gbit: 1024 Blocks per Plane x8 = 128M + 4M bytes x16 = 64M + 2M words
  • 4 Gbit: 2048 Blocks per Plane x8 = 256M + 8M bytes x16 = 128M + 4M words
  • Device Size:
  • 1 Gbit: 1 Plane per Device or 128 Mbyte
  • 2 Gbit: 2 Planes per Device or 256 Mbyte
  • 4 Gbit: 2 Planes per Device or 512 Mbyte
• NAND Flash Interface
  • Open NAND Flash Interface (ONFI) 1.0 compliant
  • Address, Data and Commands multiplexed
• Supply Voltage
  • 3.3V device: Vcc = 2.7V ~ 3.6V
• Security
  • One Time Programmable (OTP) area
  • Hardware program/erase disabled during power transition
• Additional Features
  • 2 Gb and 4 Gb parts support Multiplane Program and Erase commands
  • Supports Copy Back Program
  • 2 Gb and 4 Gb parts support Multiplane Copy Back Program
  • Supports Read Cache
• Electronic Signature
  • Manufacturer ID: 01h
• Operating Temperature
  • Industrial: -40°C to 85°C
  • Automotive: -40°C to 105°C