FIFO Mem Sync Dual Depth/Width Uni-Dir 32K x 36 128-Pin LQFP Tray

The SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, and SN74V3690 are exceptionally deep, high-speed CMOS, first-in first-out (FIFO) memories, with clocked read and write controls and a flexible bus-matching ×36/×18/×9 data flow. These FIFOs offer several key user benefits:Flexible ×36/×18/×9 bus matching on both read and write ports The period required by the retransmit operation is fixed and short. The first-word data-latency period, from the time the first word is written to an empty FIFO to the time it can be read, is fixed and short. High-density offerings up to 1 Mbit Bus-matching synchronous FIFOs are particularly appropriate for network, video, signal processing, telecommunications, data communications, and other applications that need to buffer large amounts of data and match buses of unequal sizes. Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume 36-bit, 18-bit, or 9-bit width, as determined by the state of external control pins’ input width (IW), output width (OW), and bus matching (BM) during the master-reset cycle. The input port is controlled by write-clock (WCLK) and write-enable (WEN\) inputs. Data is written into the FIFO on every rising edge of WCLK when WEN\ is asserted. The output port is controlled by read-clock (RCLK) and read-enable (REN\) inputs. Data is read from the FIFO on every rising edge of RCLK when REN\ is asserted. An output-enable (OE) input is provided for 3-state control of the outputs. The frequencies of the RCLK and WCLK signals can vary from 0 to fMAX, with complete independence. There are no restrictions on the frequency of one clock input with respect to the other. There are two possible timing modes of operation with these devices: first-word fall-through (FWFT) mode and standard mode. In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. REN\ need not be asserted for accessing the first word. However, subsequent words written to the FIFO do require a low on REN\ for access. The state of the FWFT/SI input during master reset determines the timing mode. For applications requiring more data-storage capacity than a single FIFO can provide, the FWFT timing mode permits depth expansion by chaining FIFOs in series (i.e., the data outputs of one FIFO are connected to the corresponding data inputs of the next). No external logic is required.In standard mode, the first word written to an empty FIFO does not appear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating REN\ and enabling a rising RCLK edge, shifts the word from internal memory to the data output lines. These FIFOs have five flag pins: empty flag or output ready (EF\/OR\), full flag or input ready (FF\/IR\), half-full flag (HF), programmable almost-empty flag (PAE\), and programmable almost-full flag (PAF\). The EF\ and FF\ functions are selected in standard mode. The IR\ and OR\ functions are selected in FWFT mode. HF\, PAE\, and PAF\ are always available for use, regardless of timing mode.

Choice of Memory Organizations

• SN74V3640 - 1024 × 36 Bit
• SN74V3650 - 2048 × 36 Bit
• SN74V3660 - 4096 × 36 Bit
• SN74V3670 - 8192 × 36 Bit
• SN74V3680 - 16384 × 36 Bit
• SN74V3690 - 32768 × 36 Bit

166-MHz Operation (6-ns Read/Write Cycle Time)

User-Selectable Input and Output Port Bus Sizing

• ×36 in to ×36 out
• ×36 in to ×18 out
• ×36 in to ×9 out
• ×18 in to ×36 out
• ×9 in to ×36 out

Big-Endian/Little-Endian User-Selectable Byte Representation

5-V-Tolerant Inputs

Fixed, Low, First-Word Latency

Zero-Latency Retransmit

Master Reset Clears Entire FIFO

Partial Reset Clears Data, but Retains Programmable Settings

Empty, Full, and Half-Full Flags Signal FIFO Status

Programmable Almost-Empty and Almost-Full Flags; Each Flag Can Default to One of Eight Preselected Offsets

Selectable Synchronous/Asynchronous Timing Modes for Almost-Empty and Almost-Full Flags

Program Programmable Flags by Either Serial or Parallel Means

Select Standard Timing (Using EF\ and FF\ Flags) or First-Word Fall-Through (FWFT) Timing (Using OR\ and IR\ Flags)

Output Enable Puts Data Outputs in High-Impedance State

Easily Expandable in Depth and Width

Independent Read and Write Clocks Permit Reading and Writing Simultaneously

High-Performance Submicron CMOS Technology

Available in 128-Pin Thin Quad Flat Pack (TQFP)