DSP Fixed-Point/Floating-Point 64-Bit 456MHz 3648MIPS 361-Pin NFBGA

The TMS320C6748 fixed- and floating-point DSP is a low-power applications processor based on a C674x DSP core. This DSP provides significantly lower power than other members of the TMS320C6000™ platform of DSPs.The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices with robust operating systems, rich user interfaces, and high processor performance through the maximum flexibility of a fully integrated, mixed processor solution.The device DSP core uses a 2-level cache-based architecture. The level 1 program cache (L1P) is a 32-KB direct mapped cache, and the level 1 data cache (L1D) is a 32-KB 2-way, set-associative cache. The level 2 program cache (L2P) consists of a 256-KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by other hosts in the system, an additional 128KB of RAM shared memory is available for use by other hosts without affecting DSP performance.Basic Secure Boot uses either SHA-1 or SHA-256, and AES-128 for boot image validation. Basic Secure Boot also uses AES-128 for boot image encryption. The secure boot flow employs a multilayer encryption scheme which not only protects the boot process but also offers the ability to securely upgrade boot and application software code. A 128-bit device-specific cipher key, known only to the device and generated using a NIST-800-22 certified random number generator, is used to protect customer encryption keys. When an update is needed, the customer uses the encryption keys to create a new encrypted image. Then the device can acquire the image through an external interface, such as Ethernet, and overwrite the existing code.The EMAC provides an efficient interface between the device and a network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration. The EMAC supports both MII and RMII interfaces.The Serial ATA (SATA) controller provides a high-speed interface to mass data storage devices. The SATA controller supports both SATA I (1.5 Gbps) and SATA II (3.0 Gbps).The Universal Parallel Port (uPP) provides a high-speed interface to many types of data converters, FPGAs, or other parallel devices. The uPP supports programmable data widths between 8- to 16-bits on both channels. Single-data rate and double-data rate transfers are supported as well as START, ENABLE, and WAIT signals to provide control for a variety of data converters.

375- and 456-MHz C674x Fixed-and Floating-Point VLIW DSP

C674x Instruction Set Features

• Superset of the C67x+ and C64x+ ISAs
• Up to 3648 MIPS and 2746 MFLOPS
• Byte-Addressable
• 8-Bit Overflow Protection
• Bit-Field Extract, Set, Clear
• Normalization, Saturation, Bit-Counting
• Compact 16-Bit Instructions

C674x Two-Level Cache Memory Architecture

• 32KB of L1P Program RAM/Cache
• 32KB of L1D Data RAM/Cache
• 256KB of L2 Unified Mapped RAM/Cache
• Flexible RAM/Cache Partition (L1 and L2)

Enhanced Direct Memory Access Controller 3:

• 2 Channel Controllers
• 3 Transfer Controllers
• 64 Independent DMA Channels
• 16 Quick DMA Channels
• Programmable Transfer Burst Size

TMS320C674x Floating-Point VLIW DSP Core

• Load-Store Architecture with Nonaligned Support
• 64 General-Purpose Registers
• Six ALU Functional Units
  • Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
  • Supports up to Four SP Additions Per Clock, Four DP Additions Every Two Clocks
  • Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation and Square-Root Reciprocal Approximation Operations Per Cycle
• Two Multiply Functional Units:
  • Mixed-Precision IEEE Floating-Point Multiply Supported up to:
    • 2 SP x SP - SP Per Clock
    • 2 SP x SP - DP Every Two Clocks
    • 2 SP x DP - DP Every Three Clocks
    • 2 DP x DP - DP Every Four Clocks
  • Fixed-Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples
• Instruction Packing Reduces Code Size
• All Instructions Conditional
• Hardware Support for Modulo Loop Operation
• Protected Mode Operation
• Exceptions Support for Error Detection and Program Redirection

Software Support

• TI DSPBIOS
• Chip Support Library and DSP Library

128KB of RAM Shared Memory

1.8-V or 3.3-V LVCMOS I/Os (Except for USB and DDR2 Interfaces)

Two External Memory Interfaces:

• EMIFA
  • NOR
  • NAND
  • 16-Bit SDRAM with 128-MB Address Space
• DDR2/Mobile DDR Memory Controller with one of the following:
  • 16-Bit DDR2 SDRAM with 256-MB Address Space
  • 16-Bit mDDR SDRAM with 256-MB Address Space

Three Configurable 16550-Type UART Modules:

• With Modem Control Signals
• 16-Byte FIFO
• 16x or 13x Oversampling Option

LCD Controller

Two Serial Peripheral Interfaces (SPIs) Each with Multiple Chip Selects

Two Multimedia Card/Secure Digital Card Interfaces with Secure Data I/O Interfaces

Two Master and Slave Inter-Integrated Circuits
(I²CBus)

One Host-Port Interface with 16-Bit-Wide Muxed Address and Data Bus For High Bandwidth

Programmable Real-Time Unit Subsystem

• Two Independent Programmable Real-Time Unit Cores
  • 32-Bit Load-Store RISC Architecture
  • 4KB of Instruction RAM Per Core
  • 512 Bytes of Data RAM Per Core
  • PRUSS can be Disabled via Software to Save Power
  • Register 30 of Each PRU is Exported From the Subsystem in Addition to the Normal R31 Output of the PRU Cores.
• Standard Power-Management Mechanism
  • Clock Gating
  • Entire Subsystem Under a Single PSC Clock Gating Domain
• Dedicated Interrupt Controller
• Dedicated Switched Central Resource