SRAM Chip Sync Single 1.8V 18M-Bit 1M x 18 0.45ns 165-Pin FBGA Tray

The CY7C1168KV18 is 1.8 V synchronous pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock.

• 18-Mbit density (1 M × 18, 512 K × 36)
• 550-MHz clock for high bandwidth
• Two-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz
• Available in 2.5 clock cycle latency
• Two input clocks for precise DDR timing
  • SRAM uses rising edges only
• Echo clocks simplify data capture in high-speed systems
• Data valid pin (QVLD) to indicate valid data on the output
• Synchronous internally self-timed writes
• DDR II+ operates with 2.5 cycle read latency when DOFF/ is asserted HIGH
• Operates similar to DDR I device with one cycle read latency when DOFF/ is asserted LOW
• Core VDD = 1.8 V ± 0.1 V; I/O VDDQ = 1.4 V to VDD
  • Supports both 1.5 V and 1.8 V I/O supply
• HSTL inputs and variable drive HSTL output buffers
• Available in 165-Ball FBGA package (13 × 15 × 1.4 mm)
• Offered in both Pb-free and non Pb-free packages
• JTAG 1149.1 compatible test access port
• Phase-locked loop (PLL) for accurate data placement