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SRAM Chip Sync Quad 2.5V 18M-Bit 512K x 36 3.1ns 100-Pin TQFP

The 18 Meg IS61NVP25672 product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, "no wait" state, device for networking and communications applications. They are organized as 512K words by 36 bits, fabricated advanced CMOS technology. Incorporating a "no wait" state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. may be suspended and all synchronous inputs ignored when Clock Enable, CKE is HIGH. In this state the internal device will hold their previous values. All Read, Write and Deselect cycles are initiated by the ADV input. When the ADV is HIGH the internal burst counter is incremented. New external addresses can be loaded when ADV is LOW. Write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when WE is LOW. Separate byte enables allow individual bytes to be written. A burst mode pin (MODE) defines the order of the burst sequence. When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst sequence is selected.
  • 100 percent bus utilization
  • No wait cycles between Read and Write
  • Internal self-timed write cycle
  • Individual Byte Write Control
  • Single R/W (Read/Write) control pin
  • Clock controlled, registered address, data and control
  • Interleaved or linear burst sequence control using MODE input
  • Three chip enables for simple depth expansion and address pipelining
  • Power Down mode
  • Common data inputs and data outputs
  • CKE pin to enable clock and suspend operation
  • JEDEC 100-pin TQFP package
  • Power Supply: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%)
  • JTAG Boundary Scan for PBGA packages
  • Industrial temperature available
  • Lead-free available

Мүнözдөмөлөр

Бренд ISSI
Datasheet PDF
Timing Type Synchronous
Number Of Words 512 kWords
Density 18 Mbit
Рабочая температура -40 to 85 °C
Pin Count 100
Number Of Ports 4
Mounting Surface Mount
Address B 19 Bit
Number Of 36 Bit
Number Of 36 Bit
Maximum O 475 mA
Описание продукта 20.1 x 14.1 x 1.45 mm
Maximum R 3.1 ns
Supplier TQFP
Typical O 2.5000 V
ECCN EAR99
Schedule B 8542320040
HTSN 8542320041
Страна происхождения Taiwan
Screening Level Industrial
Minimum O 2.375 V
Maximum O 2.625 V
Maximum C 200 MHz
Data Rate SDR
Architecture Pipelined
Lead Finish Tin/Lead
Max Proce 225
SKU: IS61NVP51236-200TQI