SRAM Chip Sync Dual 3.3V 18M-Bit 1M x 18 3.4ns 100-Pin TQFP Tray

The CY7C1372D is a 3.3 V, 512 K × 36 and 1 M × 18 synchronous pipelined burst SRAMs with No Bus Latency (NoBLä) logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1372D are equipped with the advanced (NoBL) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent write/read transitions. The CY7C1372D are pin compatible and functionally equivalent to ZBT devices. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the clock enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Write operations are controlled by the byte write selects (BWa–BWd for CY7C1372DV25–BWb for CY7C1372DV25) and a write enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous chip enables (CE1, CE2, CE3) and an asynchronous output enable (OE) provide for easy bank selection and output tri-state control. In order to avoid bus contention, the output drivers are synchronously tristated during the data portion of a write sequence.

• Pin-compatible and functionally equivalent to ZBT™
• Supports 250-MHz bus operations with zero wait states
• Available speed grades are 250, 200, and 167 MHz
• Internally self-timed output buffer control to eliminate the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined operation
• Byte write capability
• 3.3 V core power supply (VDD)
• 3.3 V/2.5 V I/O power supply (VDDQ)
• Fast clock-to-output times
• 2.6 ns (for 250 MHz device)
• Clock enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non Pb-free 65-ball FBGA package
• IEEE 1149.1 JTAG-compatible boundary scan
• Burst capability - linear or interleaved burst order
• “ZZ” sleep mode option and stop clock option