SRAM Chip Sync Dual 1.8V 36M-Bit 2M x 18 0.45ns 165-Pin FBGA

GS8342S18BD is a built in compliance with the SigmaSIO DDR-II SRAM pinout standard for Separate I/O synchronous SRAMs. They are 37,748,736-bit (36Mb) SRAMs. These are the first in a family of wide, very low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.

• Simultaneous Read and Write SigmaSIO™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• DLL circuitry for wide output data valid window and future frequency scaling
• Burst of 2 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ mode pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available