SRAM Chip Async Single 5V 64K-Bit 16K x 4-Bit 15ns 24-Pin SOJ T/R

The CY7C166 is a high-performance CMOS static RAMs organized as 16,384 by 4 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE) and three-state drivers. The CY7C166 has an active LOW Output Enable (OE) feature. Both devices have an automatic powerdown feature, reducing the power consumption by 65% when deselected. Writing to the device is accomplished when the Chip Enable (CE) and Write Enable (WE) inputs are both LOW (and the Output Enable (OE) is LOW for the CY7C166). Data on the four input/output pins (I/O0 through I/O3) is written into the memory location specified on the address pins (A0 through A13). Reading the device is accomplished by taking Chip Enable (CE) LOW (and OE LOW for CY7C166), while Write Enable (WE) remains HIGH. Under these conditions the contents of the memory location specified on the address pins will appear on the four data I/O pins. The I/O pins stay in a high-impedance state when Chip Enable (CE) is HIGH (or Output Enable (OE) is HIGH for CY7C166). A die coat is used to insure alpha immunity.

• High speed
  • 15 ns
• Output enable (OE) feature (CY7C166)
• CMOS for optimum speed/power
• Low active power
  • 633 mW
• Low standby power
  • 110 mW
• TTL-compatible inputs and outputs
• Automatic power-down when deselected