SRAM Chip Async Single 5V 1M-Bit 128K x 8 20ns 32-Pin TSOP-I

The CY7C109BN is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable, an active HIGH Chip Enable, an active LOW Output Enable, and three-state drivers. Writing to the device is accomplished by taking Chip Enable One and Write Enable inputs LOW and Chip Enable Two input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable One and Output Enable LOW while forcing Write Enable and Chip Enable Two HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected, the outputs are disabled, or during a write operation. The CY7C109BN is available in standard 400-mil-wide SOJ and 32-pin TSOP type I packages. The CY7C1009BN is available in a 300-mil-wide SOJ package. The CY7C1009BN and CY7C109BN are functionally equivalent in all other respects.

• High speed
  • tAA = 12 ns
• Low active power
  • 495 mW (max. 12 ns)
• Low CMOS standby power
  • 55 mW (max.) 4 mW
• 2.0V Data Retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE/ and OE1/, CE2, and options