SRAM Chip Async Single 3V 256K-Bit 32K x 8 70ns 28-Pin TSOP-I

The CY62256V is a high-performance CMOS static RAM organized as 32,768 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable and active LOW output enable and three-state drivers. This device has an automatic power-down feature, reducing the power consumption by 98% when deselected. The CY62256V is in the standard 450-mil-wide (300-mil body width) SOIC, TSOP, and reverse TSOP packages. An active LOW write enable signal controls the writing/reading operation of the memory. Reading the device is accomplished by selecting the device and enabling the outputs, chip enable and output enable active LOW, while write enable remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins is present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable is HIGH. A die coat is used to ensure alpha immunity.

• 55, 70 ns access time
• CMOS for optimum speed/power
• Wide voltage range: 2.7V-3.6V
• Low active power (70 ns, LL version)
  • 108 mW (max.)
• Low standby power (70 ns, LL version)
  • 18 µW (max.)
• Easy memory expansion with CE/ and OE/ and features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected