SRAM Chip Async Single 3.3V 4M-Bit 512K x 8 10ns 44-Pin TSOP-II Tray

CY7C1049G30 is high-performance CMOS fast static RAM devices with embedded ECC. Both devices are offered in single and dual chip-enable options and in multiple pin configurations. Data writes are performed by asserting the Chip Enable (CE\) and Write Enable (WE\) inputs LOW, while providing the data on I/O0 through I/O7 and address on A0 through A18 pins. Data reads are performed by asserting the Chip Enable (CE\) and Output Enable (OE\) inputs LOW and providing the required address on the address lines. Read data is accessible on the I/O lines (I/O0 through I/O7). All I/Os (I/O0 through I/O7) are placed in a high-impedance state during the following events: The device is deselected (CE\ HIGH), The control signal OE is de-asserted.

• High speed: tAA = 10 ns
• Low active and standby currents
  • Active current: Icc = 38 mA typical
  • Standby current: Isb2 = 6 mA typical
• Operating voltage range: 2.2 V to 3.6 V
• 1.0-V data retention
• TTL-compatible inputs and outputs
• Error indication (ERR) pin to indicate 1-bit error detection andcorrection
• Pb-free 36-pin SOJ and 44-pin TSOP II packages