SRAM Chip Async Single 1.8V 16M-Bit 1M x 16 55ns 48-Pin VFBGA

The CY62167DV18 is a high-performance CMOS static RAM organized as 1M words by 16-bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life (MoBL) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. The device can also be put into standby mode when deselected. The input/output pins are placed in a high-impedance state when: deselected, outputs are disabled, both Byte High Enable and Byte Low Enable are disabled, or during a Write operation. Writing to the device is accomplished by taking Chip Enables and Write Enable input LOW. If Byte Low Enable is LOW, then data from I/O pins, is written into the location specified on the address pins. If Byte High Enable is LOW, then data from I/O pins is written into the location specified on the address pins. Reading from the device is accomplished by taking Chip Enables and Output Enable LOW while forcing the Write Enable HIGH. If Byte Low Enable is LOW, then data from the memory location specified by the address pins appear on I/O0 to I/O7. If Byte High Enable is LOW, then data from memory appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of Read and Write modes.

• Very high speed: 55 ns
• Wide voltage range: 1.65V-1.95V
• Ultra low active power
  • Typical active current: 1.5 mA @ f = 1 MHz
  • Typical active current: 15 mA @ f = fmax
• Ultra low standby power
• Easy memory expansion with CE/ and OE1/, CE/ and OE2/, and features
• Automatic power down when deselected
• CMOS for optimum speed and power
• Available in Pb-free 48-ball VFBGA package