SRAM Chip Async Dual 5V 16K-Bit 2K x 8 55ns 52-Pin PLCC Tube

CY7C136E is high-speed, low-power CMOS 1 K / 2 K × 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C136E can be used as a standalone dual-port static RAM. It is the solution to applications requiring shared or buffered data, such as cache memory for DSP, bit-slice, or multiprocessor designs. Each port has independent control pins; chip enable (CE), write enable (R/W), and output enable (OE). Two flags are provided on each port, BUSY and INT. The BUSY flag signals that the port is trying to access the same location, which is currently being accessed by the other port. The INT is an interrupt flag indicating that data is placed in a unique location[1]. The BUSY and INT flags are push pull outputs. An automatic power-down feature is controlled independently on each port by the chip enable (CE) pins.

• True dual-ported memory cells, which allow simultaneous reads of the same memory location
• 1 K / 2 K × 8 organization
• 0.35 micron complementary metal oxide semiconductor (CMOS) for optimum speed and power
• High speed access: 15 ns
• Low operating power: ICC = 110 mA (typical), Standby: ISB3 = 0.05 mA (typical)
• Fully asynchronous operation
• Automatic power-down
• BUSY output flag to indicate access to the same location by both ports
• INT flag for port-to-port communication
• Available in 52-pin plastic leaded chip carrier (PLCC), 52-pin plastic quad flat package (PQFP)
• Pb-free packages available