SRAM Chip Async Dual 3.3V 128K-Bit 8K x 16 25ns 100-Pin TQFP

The CY7C025AV consist of an array of 4 K, 8 K, and 16 K words of 16 bits each of dual-port RAM cells, IO and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes and reads to the same location, a BUSY pin is provided on each port. Two Interrupt (INT) pins can be used for port to port communication. Two Semaphore (SEM) control pins are used for allocating shared resources. With the M/S pin, the devices can function as a master (BUSY pins are outputs) or as a slave (BUSY pins are inputs). They also have an automatic power down feature controlled by CE. Each port has its own output enable control (OE), which enables data to be read from the device.

• True dual-ported memory cells which enable simultaneous access of the same memory location
• 4, 8 or 16 K × 16 organization (CY7C025AV)
• 0.35 micron CMOS for optimum speed and power
• High speed access: 20 ns and 25 ns
• Low operating power
  • Active: ICC = 115 mA (typical)
  • Standby: ISB3 = 10 µA (typical)
• Fully asynchronous operation
• Automatic power down
• Expandable data bus to 32 bits or more using Master and Slave chip select when using more than one device
• On chip arbitration logic
• Semaphores included to permit software handshaking between ports
• INT flag for port-to-port communication
• Separate upper byte and lower byte control
• Pin select for Master or Slave (M/S)
• Commercial and industrial temperature ranges
• Available in 100-pin Pb-free TQFP and 100-pin TQFP