SRAM Chip Sync Single 3.3V 9M-Bit 256K x 36 3.5ns 100-Pin TQFP

The CY7C1354B is 3.3V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Latency (NoBL?) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1354B are equipped with the advanced (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions. The CY7C1354B are pin compatible and functionally equivalent to ZBT devices. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle.

• Pin-compatible and functionally equivalent to ZBT
• Supports 225-MHz bus operations with zero wait states
  • Available speed grades are 225, 200, and 166 MHz
• Internally self-timed output buffer control to eliminate the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined operation
• Byte Write capability
• Separate VDDQ for 3.3V or 2.5V I/O
• Single 3.3V power supply
• Fast clock-to-output times
  • 2.8 ns (for 225-MHz device)
  • 3.2ns (for 200-MHz device)
  • 3.5 ns (for 166-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Available in 100 TQFP, 119 BGA, and 165 fBGA packages
• IEEE 1149.1 JTAG Boundary Scan
• Burst capability-linear or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option