SRAM Chip Sync Quad 1.8V/2.5V 32M-Bit 1M x 32 8.5ns/4ns 165-Pin FBGA Tray
The GS832132GE is a 37,748,736-bit high performance synchronous SRA M with a 2- bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.
- IEEE 1149.1 JTAG-compatible Boundary Scan
- 2.5 V or 3.3 V +10%/–10% core power supply
- 2.5 V or 3.3 V I/O supply
- LBO pin for Linear or Interleaved Burst mode
- Internal input resistors on mode pins allow floating mode pins
- Byte Write (BW) and/or Global Write (GW) operation
- Internal self-timed write cycle
- Automatic power-down for portable applications
- JEDEC-standard 165-bump FP-BGA package
- RoHS-compliant 165-bump BGA package available
- 32MB or 36MB product family
- Green 15 mm x 17 mm, 165 FPBGA
仕様
| Brand | GSI Technology |
|---|---|
| Datasheet | |
| Timing Type | Synchronous |
| Number Of Words | 1 MWords |
| Density | 32 Mbit |
| Operating temperature | -40 to 85 °C |
| Pin Count | 165 |
| Number Of Ports | 4 |
| Mounting | Surface Mount |
| Address B | 20 Bit |
| Number Of | 32 Bit |
| Number Of | 32 Bit |
| Maximum O | 170@Flow-Through|210@Pipelined mA |
| Product description | 17 x 15 x 1.04 mm |
| Maximum R | 8.5@Flow-Through|4@Pipelined ns |
| Supplier | FBGA |
| Typical O | 1.8, 2.5 V |
| ECCN | 3A991.B.2.B |
| Schedule B | 8542320040 |
| HTSN | 8542320041 |
| Screening Level | Industrial |
| Minimum O | 1.7, 2.3 V |
| Maximum O | 2, 2.7 V |
| Maximum C | 117.6@Flow-Through|133@Pipelined MHz |
| Data Rate | SDR |
| Architecture | Flow-Through|Pipelined |
| Lead Finish | Tin/Silver/Copper |
| Max Proce | 260 |
| Msl Level | 3 |
SKU: GS832132GE-133IV