SRAM Chip Sync Octal 1.8V/2.5V 18M-Bit 256K x 72-Bit 5.5ns/3ns 209-Pin BGA Tray
SRAM Chip Sync Octal 1.8V/2.5V 18M-Bit 256K x 72-Bit 5.5ns/3ns 209-Pin BGA Tray
- FT pin for user-configurable flow through or pipeline operation
- Single/Dual Cycle Deselect selectable
- IEEE 1149.1 JTAG-compatible Boundary Scan
- ZQ mode pin for user-selectable high/low output drive
- 2.5 V or 3.3 V +10%/–10% core power supply
- LBO pin for Linear or Interleaved Burst mode
- Internal input resistors on mode pins allow floating mode pins
- Default to SCD x18/x36 Interleaved Pipeline mode
- Byte Write (BW) and/or Global Write (GW) operation
- Internal self-timed write cycle
- Automatic power-down for portable applications
- JEDEC-standard 209-bump BGA package
- RoHS-compliant 209-bump BGA package available
仕様
| Brand | GSI Technology |
|---|---|
| Datasheet | |
| Timing Type | Synchronous |
| Number Of Words | 256 kWords |
| Density | 18 Mbit |
| Operating temperature | 0 to 70 °C |
| Pin Count | 209 |
| Number Of Ports | 8 |
| Mounting | Surface Mount |
| Address B | 18 Bit |
| Number Of | 72 Bit |
| Number Of | 72 Bit |
| Maximum O | 265@Flow-Through|350@Pipelined mA |
| Product description | 22 x 14 x 1.1 mm |
| Maximum R | 5.5@Flow-Through|3@Pipelined ns |
| Supplier | BGA |
| Typical O | 1.8, 2.5 V |
| ECCN | 3A991.B.2.B |
| Schedule B | 8542320040 |
| HTSN | 8542320041 |
| Country of origin | Taiwan |
| Screening Level | Commercial |
| Minimum O | 1.7, 2.3 V |
| Maximum O | 2, 2.7 V |
| Maximum C | 181.8@Flow-Through|250@Pipelined MHz |
| Data Rate | SDR |
| Architecture | Flow-Through|Pipelined |
| Lead Finish | Tin/Lead |
SKU: GS816272CC-250V