SRAM Chip Sync Dual 3.3V 2M-Bit 128K x 18 6.5ns 100-Pin TQFP

The CY7C1324H is a 128 K × 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input. The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable , depth-expansion Chip Enables, Burst Control inputs , Write Enables , and Global Write. Asynchronous inputs include the Output Enable and the ZZ pin. The CY7C1324H allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe or the cache Controller Address Strobe inputs. Address advancement is controlled by the Address Advancement input. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor or Address Strobe Controller are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin . The CY7C1324H operates from a +3.3 V core power supply while all outputs may operate with either a +3.3 V or +2.5 V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.

• 128 K × 18 common I/O
• 3.3 V core power supply
• 3.3- / 2.5-V I/O supply
• Fast clock-to-output times
  • 6.5 ns (133 MHz version)
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Offered in JEDEC-standard Pb-free 100-pin thin quad flat pack (TQFP) package
• “ZZ” sleep mode option