SRAM Chip Sync Dual 3.3V 18M-Bit 1M x 18 6.5ns 100-Pin TQFP

The ISSI IS61LF is high-speed, low-power synchronousstatic RAMs designed to provide burstable, high performance memory for communication and network ingapplications. The IS61LF/VF25672A is organized as262,144 words by 72 bits. The IS61LF/VF51236A is organizedas 524,288 words by 36 bits. The IS61LF/VF102418Ais organized as 1,048,576 words by 18 bits. Fabricated with ISSI"s advanced CMOS technology, the device integratesa 2-bit burst counter, high-speed SRAM core, andhigh-drive capability outputs into a single monolithic circuit.All synchronous inputs pass through registers controlledby a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated bythe rising edge of the clock input. Write cycles can be oneto four bytes wide as controlled by the write control inputs.The mode pin is used to select the burst sequence order,Linear burst is achieved when this pin is tied LOW.Interleave burst is achieved when this pin is tied HIGH orleft floating.

• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and control
• Burst sequence control using MODE input
• Three chip enable option for simple depth expansionand address pipelining
• Common data inputs and data outputs
• Auto Power-down during deselect
• Single cycle deselect
• Snooze MODE for reduced-power standby
• JTAG Boundary Scan for PBGA package
• JEDEC 100-Pin TQFP, 119-pin PBGA, 209-BallPBGA and 165-pin PBGA packages
• Lead-free available