SRAM Chip Sync Dual 2.5V/3.3V 9M-Bit 512K x 18 6.5ns/3ns 100-Pin TQFP
SRAM Chip Sync Dual 2.5V/3.3V 9M-Bit 512K x 18 6.5ns/3ns 100-Pin TQFP
- FT pin for user-configurable flow through or pipeline operation
- Single Cycle Deselect (SCD) operation
- 2.5 V or 3.3 V +10%/–10% core power supply
- 2.5 V or 3.3 V I/O supply
- LBO pin for Linear or Interleaved Burst mode
- Internal input resistors on mode pins allow floating mode pins
- Default to Interleaved Pipeline mode
- Byte Write (BW) and/or Global Write (GW) operation
- Internal self-timed write cycle
- Automatic power-down for portable applications
- JEDEC-standard 100-lead TQFP package
- RoHS-compliant 100-lead TQFP package available
仕様
| Brand | GSI Technology |
|---|---|
| Datasheet | |
| Timing Type | Synchronous |
| Number Of Words | 512 kWords |
| Density | 9 Mbit |
| Operating temperature | 0 to 70 °C |
| Pin Count | 100 |
| Number Of Ports | 2 |
| Mounting | Surface Mount |
| Number Of | 18 Bit |
| Product description | 20 x 14 x 1.4 mm |
| Typical O | 2.5, 3.3 V |
| ECCN | 3A991.B.2.B |
| Schedule B | 8542320070 |
| HTSN | 8542320041 |
| Country of origin | United States |
| Screening Level | Commercial |
| Minimum O | 2.3, 3 V |
| Maximum O | 2.7, 3.6 V |
| Data Rate | SDR |
| Architecture | Flow-Through|Pipelined |
| Lead Finish | Matte Tin |
SKU: GS88018CGT-200