SRAM Chip Async Single 5V 4M-Bit 512K x 8 20ns 36-Pin SOJ

The CY7C1049B is a high-performance CMOS static RAM organized as 524,288 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable, an active LOW Output Enable, and tri-state drivers. Writing to the device is accomplished by taking Chip Enable and Write Enable inputs LOW. Data on the eight I/O pins is then written into the location specified on the address pins. Reading from the device is accomplished by taking Chip Enable and Output Enable LOW while forcing Write Enable HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins are placed in a high-impedance state when the device is deselected, the outputs are disabled, or during a write operation. The CY7C1049B is available in a standard 400-mil-wide 36-pin SOJ package with center power and ground pinout.

• High speed
  • tAA = 12 ns
• Low active power
  • 1320 mW (max.)
• Low CMOS standby power (Commercial L version)
  • 2.75 mW (max.)
• 2.0V Data Retention (400 µW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE/ and OE/ and features
• Available in Pb-free and non Pb-free 36-Lead (400-Mil) Molded SOJ