SRAM Chip Async Single 5V 256K-Bit 32K x 8 10ns 28-Pin SOJ

The CY7C199D is a high performance CMOS static RAM organized as 32,768 words by 8-bits. Easy memory expansion is provided by an active LOW chip enable (CE), an active LOW output enable (OE) and tri-state drivers. This device has an automatic power-down feature, reducing the power consumption when deselected. The input and output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW and WE LOW). Write to the device by taking chip enable (CE) and write enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A14). Read from the device by taking chip enable (CE) and output enable (OE) LOW while forcing write enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appears on the I/O pins. The CY7C199D device is suitable for interfacing with processors that have TTL I/P levels. It is not suitable for processors that require CMOS I/P levels.

• Temperature range
  • -40 °C to 85 °C
• Pin and function compatible with CY7C199C
• High speed
  • tAA = 10 ns
• Low active power
  • ICC = 80 mA at 10 ns
• Low CMOS standby power
  • ISB2 = 3 mA
• 2.0 V data retention
• Automatic power-down when deselected
• Complementary metal oxide semiconductor (CMOS) for optimum speed/power
• Transistor-transistor logic (TTL) compatible inputs and outputs
• Easy memory expansion with CE and OE features
• Available in Pb-free 28-pin 300-Mil-wide molded small outline J-lead package (SOJ) and 28-pin thin small outline package (TSOP) I packages