SRAM Chip Async Single 5V 1M-Bit 128K x 8 15ns 32-Pin SOJ

The CY7C1018V33 is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable, an active LOW Output Enable, and three-state drivers. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking Chip Enable and Write Enable inputs LOW. Data on the eight I/O pins is then written into the location specified on the address pins. Reading from the device is accomplished by taking Chip Enable and Output Enable LOW while forcing Write Enable HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins are placed in a high-impedance state when the device is deselected, the outputs are disabled, or during a write operation. The CY7C1018V33 is available in a standard 300-mil-wide SOJ and CY7C1019V33 is available in a standard 400-mil-wide package. The CY7C1018V33 and CY7C1019V33 are functionally equivalent in all other respects.

• High Speed
  • tAA = 10 ns
• CMOS for optimum Speed and Power
• Data Retention at 2.0 V
• Center Power/Ground Pinout
• Automatic Power Down when deselected
• Easy Memory Expansion with CE/ and OE/ and Options