SRAM Chip Async Single 3.3V 32M-Bit 2M x 16 70ns 48-Pin TFBGA T/R

The IS66WVE2M16EBLL is a integrated memory device containing 32Mbit Pseudo Static Random Access Memory using a self-refresh DRAM array organized as 2M words by 16 bits. The device includes several power saving modes : Partial Array Refresh mode where data is retained in a portion of the array and Deep Power Down mode. Both these modes reduce standby current drain. The die has separate power rails, VDDQ and VSSQ for the I/O to be run from a separate power supply from the device core.

• Asynchronous and page mode interface
• Dual voltage rails for optional performance
  • VDD 2.7V~3.6V, VDDQ 2.7V~3.6V
• Page mode read access
  • Interpage Read access : 60ns, 70ns
  • Intrapage Read access : 25ns
• Low Power Consumption
  • Asynchronous Operation < 30 mA
  • Intrapage Read < 23mA
  • Standby < 180 µA (max.)
  • Deep power-down (DPD)
  • ALL/CLL: < 3µA (Typ)
  • BLL: < 10µA (Typ)
• Low Power Feature
  • Temperature Controlled Refresh
  • Partial Array Refresh
  • Deep power-down (DPD) mode
• Operating temperature Range Industrial: -40°C~85°C, Automotive A1: -40°C~85°C
• Package: 48-ball TFBGA