SRAM Chip Async Single 2.5V/3.3V 2M-Bit 128K x 16 10ns 44-Pin TSOP-II T/R

The ISSI IS61WV12816DBLL are high-speed, 2,097,152-bit static RAMs organized as 131,072 words by 16 bits. It is fabricated using ISSI"s high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS61WV12816DBLL are packaged in the JEDEC standard 44-pin TSOP Type II and 48-pin Mini BGA (6mm x 8mm).

• High-speed access time: 8, 10, 12, 20 ns
• Low Active Power: 135 mW (typical)
• Low Standby Power: 12 µW (typical) CMOS standby
• Single power supply
  • VDD 2.4V to 3.6V (IS61WV12816DBLL)
• Fully static operation: no clock or refresh required
• Three state outputs
• Data control for upper and lower bytes
• Industrial and Automotive temperature support
• Lead-free available