SRAM Chip Async Dual 5V 144K-Bit 8K x 18 25ns 100-Pin TQFP

The CY7C0251 is low power CMOS 4K x 16/18 and 8K x 16/18 dual-port static RAMs. Various arbitration schemes are included on the CY7C024/ 0241 and CY7C025/0251 to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The CY7C024/ 0241 and CY7C025/0251 can be used as standalone 16 or 18-bit dual-port static RAMs or multiple devices can be combined to function as a 32-/36-bit or wider master/ slave dual-port static RAM. An M/S pin is provided for implementing 32-/36-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory.Each port has independent control pins: Chip Enable , Read or Write Enable , and Output Enable . Two flags are provided on each port . BUSY/ signals that the port is trying to access the same location currently being accessed by the other port. The Interrupt Flag permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power down feature is controlled independently on each port by a chip select pin

• True dual-ported memory cells, which allow simultaneous reads of the same memory location
• 4K x 16 organization (CY7C024/024A)
• 4K x 18 organization (CY7C0241)
• 8K x 16 organization (CY7C025)
• 8K x 18 organization (CY7C0251)
• 0.65 micron CMOS for optimum speed and power
• High speed access: 15 ns
• Low operating power: ICC = 150 mA (typ)
• Fully asynchronous operation
• Automatic power down
• Expandable data bus to 32/36 bits or more using Master/Slave chip select when using more than one device
• On-chip arbitration logic
• Semaphores included to permit software handshaking between ports
• INT/ flag for port-to-port communication
• Separate upper-byte and lower-byte control
• Pin select for Master or Slave
• Available in 84-pin (Pb-free) PLCC, 84-pin PLCC, 100-pin (Pb-free) TQFP, and 100-pin TQFP