DSP Fixed-Point/Floating-Point 32-Bit 300MHz 2400MIPS 256-Pin BGA

The C6743 device is a low-power digital signal processor based on C674x DSP core. The device consumes significantly lower power than other members of the TMS320C6000 platform of DSPs. The C6743 device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring high processing performance. The C6743 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32-KB direct mapped cache and the Level 1 data cache (L1D) is a 32-KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 128-KB of memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: a 10/100 Mbps Ethernet MAC (EMAC) with a management data input/output (MDIO) module; two I2C Bus interfaces; two multichannel audio serial ports (McASPs) with 14/9 serializers and FIFO buffers; two 64-bit general-purpose timers each configurable (one configurable as watchdog); up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; two UART interfaces (one with both RTS\ and CTS\); three enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two 32-bit enhanced quadrature encoded pulse (eQEP) peripherals; and 2 external memory interfaces (EMIFs): an asynchronous external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM. The Ethernet Media Access Controller (EMAC) provides an efficient interface between the C6743 and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration. The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides. 

Applications

• Networking
• High-Speed Encoding
• Professional Audio

Software Support

• TI DSP/BIOS
• Chip Support Library and DSP Library

375-MHz TMS320C674x Fixed- and Floating-Point VLIW DSP Core

• Load-Store Architecture with Nonaligned Support
• 64 General-Purpose Registers (32-Bit)
• Six ALU (32- and 40-Bit) Functional Units
  • Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
  • Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks
  • Supports up to Two Floating Point (SP or DP) Reciprocal Approximation and Square-Root Reciprocal Approximation Operations Per Cycle
• Two Multiply Functional Units
  • Mixed-Precision IEEE Floating Point Multiply Supported up to:
    • 2 SP x SP -> SP Per Clock
    • 2 SP x SP -> DP Every Two Clocks
    • 2 SP x DP -> DP Every Three Clocks
    • 2 DP x DP -> DP Every Four Clocks
  • Fixed-Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples
• Instruction Packing Reduces Code Size
• All Instructions Conditional
• Hardware Support for Modulo Loop
  Operation
• Protected Mode Operation
• Exceptions Support for Error Detection and Program Redirection

C674x Instruction Set Features

• Superset of the C67x+ and C64x+ ISAs
• 3000 MIPS and 2250 MFLOPS C674x
• Byte-Addressable
• 8-Bit Overflow Protection
• Bit-Field Extract, Set, Clear
• Normalization, Saturation, Bit-Counting
• Compact 16-Bit Instructions

C674x Two-Level Cache Memory Architecture

• 32KB of L1P Program RAM/Cache
• 32KB of L1D Data RAM/Cache
• 128KB of L2 Unified Mapped RAM/Cache
• Flexible RAM/Cache Partition

Enhanced Direct Memory Access Controller 3:

• 2 Transfer Controllers
• 32 Independent DMA Channels
• 8 Quick DMA Channels
• Programmable Transfer Burst Size

3.3-V LVCMOS I/Os

Two External Memory Interfaces:

• EMIFA
  • NOR (8-Bit-Wide Data)
  • NAND (8-Bit-Wide Data)
• EMIFB
  • 16-bit SDRAM, up to 128MB

Two Configurable 16550-Type UART Modules:

• UART0 with Modem Control Signals
• 16-Byte FIFO
• 16x or 13x Oversampling Option

One Serial Peripheral Interface with One Chip Select

Multimedia Card/Secure Digital

Two Master and Slave Inter-Integrated Circuit (I²CBus

Programmable Real-Time Unit Subsystem (PRUSS)

• Two Independent Programmable Real-Time Unit Cores
  • 32-Bit Load-Store RISC Architecture
  • 4KB of Instruction RAM per Core
  • 512 Bytes of Data RAM per Core
  • PRUSS can be Disabled Through Software to Save Power
  • Register 30 of each PRU is Exported from the Subsystem in Addition to the Normal R31 Output of the PRU Cores
• Standard Power-Management Mechanism
  • Clock Gating
  • Entire Subsystem Under a Single PSC Clock Gating Domain
• Dedicated Interrupt Controller
• Dedicated Switched Central Resource

Two Multichannel Audio Serial Ports:

• Supports TDM, I2S, and Similar Formats
• FIFO Buffers for Transmit and Receive

10/100 Mbps RMII Ethernet Media Access Controller:

• IEEE 802.3 Compliant (3.3-V I/O Only)