Switch Fabric 2K x 2K 1.8V/3.3V 256-Pin BGA Tray

The ZL50019 is a maximum 2,048 x 2,048 channel non-blocking digital Time Division Multiplex (TDM) switch. It has thirty-two input streams (STi0 - 31) and thirty-two output streams (STio0 - 31). The device can switch 64 kbps and Nx64 kbps TDM channels from any input stream to any output stream. Each of the input and output streams can be independently programmed to operate at any of the following data rates: 2.048, 4.096, 8.192 or 16.384 Mbps. The ZL50019 provides up to sixteen high impedance control outputs (STOHZ0 - 15) to support the use of external tristate drivers for the first sixteen output streams (STio0 - 15). The output streams can be configured to operate in bi-directional mode, in which case STi0 - 31 will be ignored. The device contains two types of internal memory - data memory and connection memory. There are four modes of operation - Connection Mode, Message Mode, BER mode and high impedance mode. In Connection Mode, the contents of the connection memory define, for each output stream and channel, the source stream and channel (the actual data to be output is stored in the data memory). In Message Mode, the connection memory is used for the storage of microprocessor data. Using Zarlink"s Message Mode capability, microprocessor data can be broadcast to the data output streams on a per-channel basis. This feature is useful for transferring control and status information for external circuits or other TDM devices. In BER mode the output channel data is replaced with a pseudorandom bit sequence (PRBS) from one of 32 PRBS generators that generates a 215-1 pattern. On the input side channels can be routed to one of 32 bit error detectors. In high impedance mode the selected output channel can be put into a high impedance state. When the device is operating as a timing master, the internal digital PLL is in use. In this mode, an external 20.000 MHz crystal is required for the on-chip crystal oscillator. The DPLL is phase-locked to one of four input reference signals (which can be 8 kHz, 1.544 MHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz provided on REF0 - 3). The on-chip DPLL operates in normal, holdover or free run mode and offers jitter attenuation. The jitter attenuation function exceeds the Stratum 4E specification.

• 2048 channel x 2048 channel non-blocking digital Time Division Multiplex (TDM) switch at 8.192 and 16.384 Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and 16.384 Mbps
• 32 serial TDM input, 32 serial TDM output streams
• Integrated Digital Phase-Locked Loop (DPLL) exceeds Telcordia GR-1244-CORE Stratum 4E specifications
• Output clocks have less than 1 ns of jitter (except for the 1.544 MHz output)
• DPLL provides holdover, free run and jitter attenuation features with four independent reference source inputs
• Exceptional input clock cycle to cycle variation tolerance (20 ns for all rates)
• Output streams can be configured as bidirectional for connection to backplanes
• Per-stream input and output data rate conversion selection at 2.048, 4.096, 8.192 or 16.384 Mbps. Input and output data rates can differ
• Per-stream high impedance control outputs (STOHZ) for 16 output streams
• Per-stream input bit delay with flexible sampling point selection
• Per-stream output bit and fractional bit advancement
• Per-channel ITU-T G.711 PCM A-Law/?-Law Translation
• Four frame pulse and six reference clock outputs
• Three programmable delayed frame pulse outputs
• Input clock: 4.096 MHz, 8.192 MHz, 16.384 MHz
• Input frame pulses: 61 ns, 122 ns, 244 ns
• Per-channel constant or variable throughput delay for frame integrity and low latency applications
• Per Stream (32) Bit Error Rate Test circuits complying to ITU-O.151
• Per-channel high impedance output control
• Per-channel message mode
• Control interface compatible with Intel and Motorola 16-bit non-multiplexed buses
• Connection memory block programming
• Supports ST-BUS and GCI-Bus standards for input and output timing
• IEEE-1149.1 (JTAG) test port
• 3.3 V I/O with 5 V tolerant inputs; 1.8 V core voltage