SRAM Chip Sync Single 2.5V/3.3V 9M-Bit 256K x 36 5ns/2.5ns 100-Pin TQFP Tray

The GS88136C(T/D) is a 9,437,184-bit high performance synchronous SRAM with a 2- bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.

• IEEE 1149.1 JTAG-compatible Boundary Scan
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP and 165-bump BGA packages
• RoHS-compliant 100-lead TQFP and 165-bump BGA packages available