SRAM Chip Sync Quad 2.5V/3.3V 72M-Bit 2M x 36 6.5ns/3ns 165-Pin FBGA Tray
SRAM Chip Sync Quad 2.5V/3.3V 72M-Bit 2M x 36 6.5ns/3ns 165-Pin FBGA Tray
- FT pin for user-configurable flow through or pipeline operation
- Single/Dual Cycle Deselect selectable
- IEEE 1149.1 JTAG-compatible Boundary Scan
- ZQ mode pin for user-selectable high/low output drive
- 2.5 V or 3.3 V +10%/–10% core power supply
- 2.5 V or 3.3 V I/O supply
- LBO pin for Linear or Interleaved Burst mode
- Internal input resistors on mode pins allow floating mode pins
- Default to SCD x18/x36 Interleaved Pipeline mode
- Byte Write (BW) and/or Global Write (GW) operation
- Internal self-timed write cycle
- Automatic power-down for portable applications
- JEDEC-standard 165-bump BGA package
- RoHS-compliant 165-bump BGA package available
- 15 mm x 17 mm, 165 FPBGA
Specifications
| Brand | GSI Technology |
|---|---|
| Datasheet | |
| Timing Type | Synchronous |
| Number Of Words | 2 MWords |
| Density | 72 Mbit |
| Operating temperature | 0 to 70 °C |
| Pin Count | 165 |
| Number Of Ports | 4 |
| Mounting | Surface Mount |
| Address B | 21 Bit |
| Number Of | 36 Bit |
| Number Of | 36 Bit |
| Maximum O | 270@Flow-Through|345@Pipelined mA |
| Product description | 17 x 15 x 1.04 mm |
| Maximum R | 6.5@Flow-Through|3@Pipelined ns |
| Supplier | FBGA |
| Typical O | 2.5, 3.3 V |
| ECCN | 3A991.B.2.B |
| Schedule B | 8542320040 |
| HTSN | 8542320041 |
| Country of origin | Taiwan |
| Screening Level | Commercial |
| Minimum O | 2.3, 3 V |
| Maximum O | 2.7, 3.6 V |
| Maximum C | 153.8@Flow-Through|200@Pipelined MHz |
| Data Rate | SDR |
| Architecture | Flow-Through|Pipelined |
| Lead Finish | Tin/Lead |
| Msl Level | 3 |
SKU: GS864436E-200