SRAM Chip Sync Dual 1.8V/2.5V 36M-Bit 2M x 18 5ns/3ns 100-Pin TQFP
SRAM Chip Sync Dual 1.8V/2.5V 36M-Bit 2M x 18 5ns/3ns 100-Pin TQFP
- FT pin for user-configurable flow through or pipeline operation
- Dual Cycle Deselect (DCD) operation
- 2.5 V or 3.3 V +10%/–10% core power supply
- 2.5 V or 3.3 V I/O supply
- LBO pin for Linear or Interleaved Burst mode
- Internal input resistors on mode pins allow floating mode pins
- Default to Interleaved Pipeline mode
- Byte Write (BW) and/or Global Write (GW) operation
- Internal self-timed write cycle
- Automatic power-down for portable applications
- RoHS-compliant 100-lead TQFP package available
Specifications
| Brand | GSI Technology |
|---|---|
| Datasheet | |
| Timing Type | Synchronous |
| Number Of Words | 2 MWords |
| Density | 36 Mbit |
| Operating temperature | 0 to 85 °C |
| Pin Count | 100 |
| Number Of Ports | 2 |
| Mounting | Surface Mount |
| Address B | 21 Bit |
| Number Of | 18 Bit |
| Number Of | 18 Bit |
| Maximum O | 245@Flow-Through|345@Pipelined mA |
| Product description | 20 x 14 x 1.4 mm |
| Maximum R | 5@Flow-Through|3@Pipelined ns |
| Supplier | TQFP |
| Typical O | 1.8, 2.5 V |
| ECCN | 3A991.B.2.B |
| Schedule B | 8542320040 |
| HTSN | 8542320041 |
| Country of origin | Taiwan |
| Screening Level | Commercial |
| Minimum O | 1.7, 2.3 V |
| Maximum O | 2, 2.7 V |
| Maximum C | 200@Flow-Through|333@Pipelined MHz |
| Data Rate | SDR |
| Architecture | Flow-Through|Pipelined |
SKU: GS8320E18AGT-333