SRAM Chip Sync Dual 1.8V 36M-Bit 1M x 36 0.5ns 165-Pin FBGA Tray

The GS8342Q36AGE are built in compliance with the Sigma Quad-II SRAM pin out standard for Separate I/O synchronous SRAMs. They are 37,748,736-bit (36Mb) SRAMs. The GS8342Q36AGE Sigma Quad SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.

• Simultaneous Read and Write Sigma Quad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write (x36, x18, and x9) and Nibble Write (x8) function
• Burst of 2 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
• Pin-compatible with present 9Mb and 18Mb and future 72Mb and 144Mb devices