SRAM Chip Async Single 5V 1M-Bit 128K x 8 15ns 32-Pin SOJ

The CY7C109B/CY7C1009B is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable , an active HIGH Chip Enable, an active LOW Output Enable, and tri-state drivers. Writing to the device is accomplished by taking Chip Enable One and Write Enable inputs LOW and Chip Enable Two input HIGH. Data on the eight I/O pins is then written into the location specified on the address pins. Reading from the device is accomplished by taking Chip Enable One and Output Enable LOW while forcing Write Enable and Chip Enable Two HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins are placed in a high-impedance state when the device is deselected, the outputs are disabled, or during a write operation. CY7C109B is available in standard 400-mil-wide SOJ and 32- pin TSOP type I packages. The CY7C1009B is available in a 300-mil-wide SOJ package. The CY7C109B and CY7C1009B are functionally equivalent in all other respects.

• High speed
  • tAA = 12 ns
• Low active power
  • 495 mW (max.)
• Low CMOS standby power
  • 11 mW (max.) (L Version)
• 2.0V Data Retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE/ and OE1/, CE/ and OE2/, and options
• CY7C109B is available in standard 400-mil-wide SOJ and 32-pin TSOP type I packages. The CY7C1009B is available in a 300-mil-wide SOJ package