SRAM Chip Async Single 3.3V 2M-Bit 128K x 16 12ns 44-Pin TSOP-II

The IS61WV12816BLL are high-speed, 2,097,152-bit static RAM organized as 131,072 words by 16 bits. They are fabricated using high performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 12 ns with low power consumption. When CE is HIGH (deselected), the device assumes a standby mode at which the power dpation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS61WV12816BLL are packaged in the JEDEC standard 44-pin TSOP (Type II) and 48-pin mini BGA (6mm x 8mm) .

• High-speed access time: 3.3V + 10%
• Operating Current: 25mA (typ.)
• Stand by Current: 400µA(typ.)
• TTL and CMOS compatible interface levels
• Fully static operation: no clocks or refresh required
• Three state outputs
• Data control for upper and lower bytes
• Commercial and Industrial temperatures available
• Lead-free available.