SRAM Chip Async Single 2.5V/3.3V 4M-Bit 512K x 8 45ns 32-Pin TSOP-I
The IS62WV5128DALL are high-speed, 4M bit static RAMs organized as 512K words by 8 bits. It is fabricated using high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high performance and low power consumption devices. When CS1\ is HIGH (deselected) the device assumes a standby mode at which the power dpation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE/) controls both writing and reading of the memory. The IS62WV5128DALL and IS62WV5128DBLL are packaged in the JEDEC standard 32-pin TSOP (TYPE I), 32-pins TSOP (TYPE I), 32-pin TSOP (Type II), 32-pin SOP and 36-pin mini BGA.
- High-speed access time: 35, 45, 55 ns
- CMOS low power operation
- 36 mW (typical) operating
- 9 µW (typical) CMOS standby
- TTL compatible interface levels
- Single power supply: 2.3V - 3.6V Vdd
- Fully static operation: no Clock or refresh required
- Three state outputs
- Industrial and Automotive temperature support
- Lead-free available
Specifications
| Brand | ISSI |
|---|---|
| Datasheet | |
| Timing Type | Asynchronous |
| Number Of Words | 512 kWords |
| Density | 4 Mbit |
| Operating temperature | -40 to 85 °C |
| Pin Count | 32 |
| Number Of Ports | 1 |
| Mounting | Surface Mount |
| Address B | 19 Bit |
| Number Of | 8 Bit |
| Number Of | 8 Bit |
| Maximum O | 20 mA |
| Product description | 8 x 20 x 1 mm |
| Maximum R | 45 ns |
| Supplier | TSOP-I |
| Typical O | 2.5, 3.3 V |
| ECCN | EAR99 |
| Schedule B | 8542320040 |
| HTSN | 8542320041 |
| Country of origin | Taiwan |
| Screening Level | Industrial |
| Minimum O | 2.3 V |
| Maximum O | 3.6 V |
| Data Rate | SDR |
| Lead Finish | Matte Tin |
| Max Proce | 260 °C |
| Msl Level | 3 |
SKU: IS62WV5128DBLL-45TLI