FIFO Mem Sync Dual Width Uni-Dir 512 x 18 56-Pin SSOP Tube

The SN74ALVC7803 FIFO is suited for buffering asynchronous data paths at 50-MHz clock rates and 13-ns access times and is designed for 3-V to 3.6-V VCC operation. The 56-pin shrink small-outline (DL) package offers greatly reduced board space over DIP, PLCC, and conventional SOIC packages. Two devices can be configured for bidirectional data buffering without additional logic. The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up.

Operates at 3-V to 3.6-V V_CC

Free-Running Read and Write Clocks Can Be Asynchronous orCoincident

Read and Write Operations Synchronized to Independent SystemClocks

Low-Power Advanced CMOS Technology

Half-Full Flag and Programmable Almost-Full/Almost-Empty Flag

Bidirectional Configuration and Width Expansion WithoutAdditional Logic

Input-Ready Flag Synchronized to Write Clock

Output-Ready Flag Synchronized to Read Clock

Fast Access Times of 13 ns With a 50-pF Load and All DataOutputs Switching Simultaneously

Data Rates From 0 to 50 MHz

Pin Compatible With SN74ACT7803

Packaged in Shrink Small-Outline 300-mil Package (DL) Using25-mil Center-to-Center Lead Spacing