FIFO Mem Sync Dual Depth/Width Uni-Dir 2K x 9 64-Pin TQFP Tray

The SN74ACT7807 is a 2048-word by 9-bit FIFO with high speed and fast access times. It processes data at rates up to 67 MHz and access times of 12 ns in a bit-parallel format. Data outputs are noninverting with respect to the data inputs. Expansion is easily accomplished in both word width and word depth. The write-clock (WRTCLK) and read-clock (RDCLK) inputs should be free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when the write-enable (WRTEN1/DP9, WRTEN2) inputs are high and the input-ready (IR) flag output is high. Data is read from memory on the rising edge of RDCLK when the read-enable (RDEN1, RDEN2) and output-enable (OE) inputs are high and the output-ready (OR) flag output is high. The first word written to memory is clocked through to the output buffer regardless of the levels on RDEN1, RDEN2, and OE. The OR flag indicates that valid data is present on the output buffer. The FIFO can be reset asynchronous to WRTCLK and RDCLK. RESET must be asserted while at least four WRTCLK and four RDCLK cycles occur to clear the synchronizing registers. Resetting the FIFO initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up. The SN74ACT7807 is characterized for operation from 0°C to 70°C.

Free-Running Read and Write Clocks Can Be Asynchronous or Coincident

Read and Write Operations Synchronized to Independent System Clocks

Input-Ready Flag Synchronized to Write Clock

Output-Ready Flag Synchronized to Read Clock

2048 Words by 9 Bits

Low-Power Advanced CMOS Technology

Programmable Almost-Full/Almost-Empty Flag

Input-Ready, Output-Ready, and Half-Full Flags

Cascadable in Word Width and/or Word Depth

Fast Access Times of 12 ns With a 50-pF Load

Data Rates up to 67 MHz

3-State Outputs

Package Options Include 44-Pin Plastic Leaded Chip Carrier (FN) and 64-Pin Thin Quad Flat (PAG, PM) Packages