SRAM Chip Sync Single 1.8V 72M-bit 2M x 36 0.45ns 165-Pin FBGA Tray

The CY7C1521KV18 is 1.8 V Synchronous Pipelined SRAM equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a two-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided.

• 72-Mbit Density (2 M × 36)
• 250 MHz Clock for High Bandwidth
• 4-word Burst for reducing Address Bus Frequency
• Double Data Rate (DDR) Interfaces (data transferred at 500 MHz) at 250 MHz
• Two Input Clocks (K and K) for precise DDR Timing
  • SRAM uses rising edges only
• Two Input Clocks for Output Data (C and C) to minimize Clock Skew and Flight Time mismatches
• Echo Clocks (CQ and CQ) simplify Data Capture in High Speed Systems
• Synchronous Internally Self-timed Writes